This application relies for priority upon Korean Patent Application No. 2001-006812, filed on Feb. 12, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention generally relates to a semiconductor device having a multi-layer copper line. More specifically, the present invention is directed to a semiconductor device in which upper and lower layers are copper lines and a via contact hole is formed therebetween.
2. Description of the Related Art
As the integration density of semiconductor devices increases, circuit lines become more complex, making it difficult to layout and construct these complex circuits on just a single device layer. Accordingly, multi-layer circuit lines and patterns are used to achieve the desired performance result.
While tungsten may be employed as a conductive material for the circuit line, due to its ability to provide high step coverage necessitated by the increasing aspect ratios of present devices, the material of choice for the circuit lines is still aluminum. Despite its many advantages, the aluminum cannot completely fill a contact hole having a high aspect ratio.
Also, generally in high-integration semiconductor devices, the metal line width is reduced while the circuit line distance remains unchanged. As such, short circuits may result from electro-migration (EM) and circuit line resistance may increase. In effect, high-integration semiconductor devices suffer from circuit line resistance and contact resistance problems that do not occur in low-integration semiconductor devices.
To overcome the foregoing problems, copper has been employed as a circuit line material for semiconductor devices. Compared to aluminum, copper has a lower resistance, which mitigates the circuit line resistance and thereby increases the reliability of semiconductor products. Unfortunately, copper is not ideally suited for conventional semiconductor device patterning processes because the etchability of copper is lower than that of aluminum. In addition, copper is easily diffused into silicon and silicon oxide layers, resulting in short circuits or increases in leakage current and parasitic capacitance.
Various approaches have been developed for solving the problems that are caused by the use of copper as a circuit line conductor. One process is known as a damascene process. In the damascene process, a lower layer is etched to form a recess therein. Copper is deposited and planarized using a chemical mechanical polishing (CMP) technique such that the copper only remains in the recess. Thus, it is not necessary to directly pattern the copper. In order to solve the diffusion problem, a method of depositing a thin diffusion barrier layer and then forming the copper can be used.
Referring to FIG. 1, semiconductor devices (not shown for simplicity) are formed on a substrate 10 through a plurality of conventional fabrication processes. A first interlayer insulating layer 11 is formed to cover these devices, which devices will later connect to a circuit line. Accordingly, the first interlayer insulating layer 11 is patterned to form a contact hole for connecting the devices and the circuit line. A thin barrier layer 13 is then formed on the first interlayer insulating layer 11 containing the contact hole. A lower metal line 15 and a contact 17 are formed on the barrier layer 13. A thin barrier layer 19 is formed over the lower metal line 15. A second interlayer insulating layer 21 is then formed on the barrier layer 19. The metal line 15, the barrier layer 19, and the second interlayer insulating layer 21 are made of copper, silicon nitride, and silicon oxide, respectively.
Referring to FIG. 2, the upper surface of the second interlayer insulating layer 21 is patterned to form a recess for an upper metal line 25. More specifically, using a photoresist, openings for the recess are partially patterned to form a via hole. In this case, the barrier layer 19 is also etched to expose a part of the lower metal line 15. A barrier layer 23 is deposited to cover the recess and the sidewall and bottom of the via hole. Copper is then deposited to fill the recess and the via hole. Using a CMP process, the remaining barrier layer and the copper layer are removed to form a via contact and an upper metal line.
In such a multi-layer circuit line using copper, the barrier layer 23 is interposed between the lower metal line 15 and the upper metal line 25 including the copper layer of the via contact. With reference to the current flow, the barrier layer 23 is serially connected between the copper layers (lower metal line 15 and upper metal line 25). The barrier layer 23 is typically made of tantalum or tantalum nitride. Since the conductivity of tantalum or tantalum nitride is lower than that of copper, the resistance at the via contact interface becomes high.
Also, in the copper line, the density and current resistance become high, creating heat which causes electro-migration (EM). As the contact area is reduced in high integration devices, the current density in a via or a contact becomes higher than that in each layer line. The resulting EM can result in an open circuit. In some cases, the EM is intensified by a so-called current crowding phenomenon, in which the current density is crowded (or accumulates) at a corner where the layer line and the via contact intersect at a right angle.
Another problem is that in addition to the barrier layer preventing uniform connection of each layer copper line to a via contact, voids can be created during the formation of the layer.
Methods for solving the above-mentioned barrier layer problems are disclosed in Korea Patent Publication No. 1999-029770 and Japan Patent Publication No. 10-261715. According to these methods, a lower copper line, a via hole, and a barrier layer are sequentially formed. The resulting structure is then etched back to remove the barrier layer on a bottom of the via hole. However, since the etch-back technique removes the horizontally formed barrier layer on the bottom of an upper copper line in a dual damascene process, another barrier layer must previously have been deposited for preventing diffusion of the upper copper line.
It is therefore an object of the present invention to provide a semiconductor device which only removes a barrier layer at an interface between an upper copper line and a copper via contact, and a method of forming the same.
It is another object of the present invention to provide a semiconductor device which can prevent electro-migration, and a method of forming the same.
It is still another object of the present invention to provide a semiconductor device which can lower a resistance of a via contact interface at a multi-layer copper line, and a method of forming the same.
It is yet another object of the present invention to provide a semiconductor device which can increase product reliability and improve product characteristics by decreasing circuit resistance, and a method of forming the same.
According to an aspect of the invention, a semiconductor device is provided in which a lower copper line is formed on a substrate, an interlayer insulating layer is formed on the lower copper line, and an upper copper line is formed on the interlayer insulating layer. A copper via contact is formed within the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed only at a bottom portion of the concave recess, wherein the lower copper line and the copper via contact are electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.
According to another aspect of the invention, there is provided a method of forming a semiconductor device having a multi-layer line, including forming an insulating layer on a substrate containing circuit devices, forming a lower copper line on the insulating layer, and forming an interlayer insulating layer on the lower copper line. The interlayer insulating layer is patterned to form a groove in an upper surface thereof, and a via contact hole is formed in a lower surface of the groove, thereby exposing a portion of the lower copper line. A concave recess is formed at the exposed portion of the lower copper line, the concave recess being vertically aligned with, and arranged below, the via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, along a sidewall of the via contact, and along the bottom surface and sides of the groove. The groove and the via contact are filled with copper to form an upper copper line, and thereby electrically connecting the upper copper line, the via contact and the lower copper line.